Hi Thaison,
On Tue, Feb 06, 2024 at 09:37:47PM -0500, Thaison Phan wrote:
> Hi,
>
> The aarch64 bootm image handler for barebox can choose a load address
> that is not 4KB aligned. This can result in unexpected behavior with
> the ADRP instruction that is available in 64 bit ARM architectures.
> ADRP forms a PC-relative address to a 4KB page where the bottom 12
> bits of the current PC will be masked out. When the load address of
> the barebox image is not 4KB aligned ADRP can end up forming an
> address that starts from an invalid page of memory or the wrong page
> of memory that was expected to be formed. The following patch aligns
> the load address for the next barebox image to be 4KB aligned to
> accommodate the ADRP instruction.
>
> Thanks,
> Thaison
>
> ---
> arch/arm/lib64/armlinux.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
> index 8382ffdf1b..d66963dae5 100644
> --- a/arch/arm/lib64/armlinux.c
> +++ b/arch/arm/lib64/armlinux.c
> @@ -43,6 +43,8 @@ static struct image_handler aarch64_fit_handler = {
> .filetype = filetype_oftree,
> };
>
> +#define ADRP_PAGE_MASK 0x1000
> +
> static int do_bootm_barebox(struct image_data *data)
> {
> void (*fn)(unsigned long x0, unsigned long x1, unsigned long x2,
> @@ -55,7 +57,7 @@ static int do_bootm_barebox(struct image_data *data)
> if (ret)
> goto out;
>
> - barebox = start;
> + barebox = ALIGN(start, ADRP_PAGE_MASK);
I'd suggest using PAGE_ALIGN here.
While I agree that the barebox image must be page aligned to be
correctly started, I wonder how it can happen that the address returned
from memory_bank_first_find_space() is not page aligned. Normally this
should be the start address of your DRAM. How comes this address is not
aligned in your case?
Sascha
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