On Mon, Jan 30, 2023 at 11:27:27AM +0100, Sascha Hauer wrote:
> This takes around 5 times too long on a i.MX8MM and around 50 times too
> long on a i.MX6Q. This was measured under a regular barebox on the
> shell. In an early environment with MMU disabled it takes 730 times too
> long.
Yikes! I'm glad I broke this in to its own patch then. :)
I did copy this code from these boards:
arch/arm/boards/cm-fx6/lowlevel.c
arch/arm/boards/skov-imx6/lowlevel.c
arch/arm/boards/technexion-wandboard/lowlevel.c
arch/arm/mach-imx/xload-gpmi-nand.c
arch/arm/mach-imx/imx6-mmdc.c (uses 1000 loops)
Maybe it's time for an i.MX6-wide early udelay?
Though this code might break if its timing is already wrong.
> Maybe we could do this:
>
> static void __udelay(void *base, int us)
> {
> int i;
>
> for (i = 0; i < us * 4; i++)
> readb(base);
> }
>
> The time spent for a register read depends on the bus clock which
> doesn't change that much between the different SoCs.
This seems like a better solution if you've tested it, I'm not too sure
how to check this. Would I just then specify the controller as the base?
Though the actual goal of the code is to wait for the controller to bestable.
Maybe there's a better way than a delay?
>
> Sascha
John.
