Hello Oleksij, On 11/19/19 10:41 AM, Oleksij Rempel wrote: > Am 19.11.19 um 09:26 schrieb Ahmad Fatoum: >> I am asking because I am testing use of the generic ARM board as default >> second stage image for the multi-image AT91s. The board specific entry point >> generates only the PBL, which runs in SRAM to do DRAM setup and chainloads >> the generic dt barebox from MMC to start of SDRAM and then calls it along >> with the dtb. > > Hm.. Is it possible that you can get an exception vector in the star of SDRAM? Not when I chainload a barebox PBL. In that case, __barebox_arm_head is the start of SDRAM and when barebox reconfigures the vector table, it will be some bytes after that. The exceptions vectors before barebox configures them are probably 0x0 because the ROM code didn't change it. Why are you asking? Cheers Ahmad -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
