Am Dienstag, den 02.02.2016, 12:17 +0100 schrieb Philipp Zabel: > The KSZ9031 erratum #2 stats: > The 125MHz reference clock (CLK125_NDO pin) output > has duty cycle variation when the KSZ9031 links up in > 1000Base-T Slave mode, resulting in wide variation on > the falling clock edge. > > The recommended workaround is to either only use the rising edge of > the CLK125_NDO output for PLL locking, or to > > Set KSZ9031 to always link up in 1000Base-T Master mode > by setting register 9h, bits [12:11] to '11'. > > Since we can't guarantee the former, this patch does the latter. > Original patch by Markus Niebel <Markus.Niebel@xxxxxx>. > > Signed-off-by: Markus Niebel <Markus.Niebel@xxxxxx> > Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> Please disregard this one. If in fact the PLL can lock only to the rising CLK125_NDO edge, we shouldn't force master mode unconditionally. This should probably only be enabled by a boolean device tree property. regards Philipp _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
