The KSZ9031 erratum #2 stats:
The 125MHz reference clock (CLK125_NDO pin) output
has duty cycle variation when the KSZ9031 links up in
1000Base-T Slave mode, resulting in wide variation on
the falling clock edge.
The recommended workaround is to either only use the rising edge of
the CLK125_NDO output for PLL locking, or to
Set KSZ9031 to always link up in 1000Base-T Master mode
by setting register 9h, bits [12:11] to '11'.
Since we can't guarantee the former, this patch does the latter.
Original patch by Markus Niebel <Markus.Niebel@xxxxxx>.
Signed-off-by: Markus Niebel <Markus.Niebel@xxxxxx>
Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
---
drivers/net/phy/micrel.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index e8a566d..5227dfb 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -220,6 +220,7 @@ static int ksz9031_config_init(struct phy_device *phydev)
"txd2-skew-ps", "txd3-skew-ps"
};
static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
+ int rc;
if (!of_node && dev->parent->device_node)
of_node = dev->parent->device_node;
@@ -242,6 +243,14 @@ static int ksz9031_config_init(struct phy_device *phydev)
tx_data_skews, 4);
}
+ rc = phy_read(phydev, MII_CTRL1000);
+ if (rc >= 0) {
+ u16 val = rc;
+ /* Enable master mode, config & prefer master */
+ val |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
+ phy_write(phydev, MII_CTRL1000, val);
+ }
+
return ksz9031_center_flp_timing(phydev);
}
--
2.7.0.rc3
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