As stated in section 29.19.32 of SAMA5D3 Series datasheet, to move from CS(n) to CS(n+1) the stride is 0x14 and not 0x10. For this reason, I was unable to use the NAND memory on my board (CS configuration was not applied and the timings were wrong). This patch fixes the problem. Matteo
From 6c26d7c00005cbf4470017a6d5361a346981bbe5 Mon Sep 17 00:00:00 2001 From: Matteo Fortini <matteo.fortini@xxxxxxxxx> Date: Wed, 28 May 2014 19:00:42 +0200 Subject: [PATCH] sama5d3x: fix AT91_SMC_CS offset stride --- arch/arm/mach-at91/sam9_smc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index a137da4..65c4558 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -16,7 +16,11 @@ #include <mach/at91sam9_smc.h> +#ifdef CONFIG_ARCH_SAMA5D3 +#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x14)) +#else #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10)) +#endif static void __iomem *smc_base_addr[2]; -- 2.0.0.rc2
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