Signed-off-by: Krzysztof Hałasa <khc@xxxxxxxxx> --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -132,11 +132,15 @@ ENTRY(v4_dma_clean_range) * * - start - virtual start address * - end - virtual end address + * + * XScale processors don't support "clean+invalidate D entry" + * (mcr p15, 0, r0, c7, c14, 1). */ .section .text.v4_dma_flush_range ENTRY(v4_dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 -1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
