From: Juergen Beisert <juergen@xxxxxxxxxxxxxx> This is required in order to enable booting from NAND and using the generic S3C2440 setup routines. Signed-off-by: Juergen Beisert <juergen@xxxxxxxxxxxxxx> --- arch/arm/boards/mini2440/config.h | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/boards/mini2440/config.h b/arch/arm/boards/mini2440/config.h index a664017..1edd69c 100644 --- a/arch/arm/boards/mini2440/config.h +++ b/arch/arm/boards/mini2440/config.h @@ -26,6 +26,28 @@ */ #define S3C24XX_CLOCK_REFERENCE 12000000 +/** + * Define the main clock configuration to be used in register CLKDIVN + * + * We must limit the frequency of the connected SDRAMs with the clock ratio + * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz + */ +#define BOARD_SPECIFIC_CLKDIVN 0x05 + +/** + * Define the MPLL configuration to be used in register MPLLCON + * + * We want the MPLL to run at 405.0 MHz + */ +#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1) + +/** + * Define the UPLL configuration to be used in register UPLLCON + * + * We want the UPLL to run at 48.0 MHz + */ +#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2) + /* * Flash access timings * Tacls = 0ns (but 20ns data setup time) -- 1.7.2.3 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
