From: Juergen Beisert <juergen@xxxxxxxxxxxxxx>
There is no rule how to connect the SDRAMs to the two clocks signales the CPU
provides. Some boards are using them on a per bank base, some others on a per
chip base. So, the check for the enabled second clock cannot be used to detect
if the second SDRAM bank is populated.
A better way is to check the MT bits of the second SDRAM bank register. When
the init code sets these bits to '00' the second bank is not used for SDRAM
and gets ignored.
Signed-off-by: Juergen Beisert <juergen@xxxxxxxxxxxxxx>
---
arch/arm/mach-s3c24xx/generic.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c
index c04e0b6..4c7e799 100644
--- a/arch/arm/mach-s3c24xx/generic.c
+++ b/arch/arm/mach-s3c24xx/generic.c
@@ -181,8 +181,9 @@ int s3c24xx_dump_clocks(void)
printf("hclk: %7d kHz\n", s3c24xx_get_hclk() / 1000);
printf("pclk: %7d kHz\n", s3c24xx_get_pclk() / 1000);
printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
- if (!(readl(MISCCR) & (1 << 18)))
- printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2, s3c24xx_get_hclk() / 1000000);
+ if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2,
+ s3c24xx_get_hclk() / 1000000);
return 0;
}
--
1.7.2.3
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