Hi Guenter, Greg,
Am Dienstag, 20. Januar 2015, 06:24:13 schrieb Guenter Roeck:
> Error log:
> drivers/clk/rockchip/clk-rk3188.c:215:50: error: macro "PLL" passed 11
> arguments, but takes just 10 RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
> ^
> drivers/clk/rockchip/clk-rk3188.c:214:11: error: 'PLL' undeclared here (not
> in a function) [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0,
> RK2928_PLL_CON(0), ^
> drivers/clk/rockchip/clk-rk3188.c:217:38: error: macro "PLL" passed 11
> arguments, but takes just 10 RK2928_MODE_CON, 4, 4, 0, NULL),
> ^
> drivers/clk/rockchip/clk-rk3188.c:219:71: error: macro "PLL" passed 11
> arguments, but takes just 10 RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE,
> rk3188_pll_rates), ^ drivers/clk/rockchip/clk-rk3188.c:221:72: error: macro
> "PLL" passed 11 arguments, but takes just 10 RK2928_MODE_CON, 12, 7,
> ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), ^ make[3]: ***
> [drivers/clk/rockchip/clk-rk3188.o] Error 1
>
> Caused by patch 'clk: rockchip: fix rk3066 pll lock bit location'.
Commit 4f8a7c549f37 ("clk: rockchip: add ability to specify pll-specific flags")
changed the number of arguments of the macro before the failing commit. So
either this commit must be present too, or the "0" elements before the
rkxxxx_pll_rates argument removed.
Below is the failing commit adapted to the 3.18 environment
Heiko
------------ 8< ---------------------------
From: Heiko Stuebner <heiko@xxxxxxxxx>
Date: Wed, 24 Dec 2014 14:31:06 +0100
Subject: [PATCH] clk: rockchip: fix rk3066 pll lock bit location
The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.
The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.
Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki <naobsd@xxxxxxxxx>
---
drivers/clk/rockchip/clk-rk3188.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index b32fcda..7eb684c 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
PNAME(mux_mac_p) = { "gpll", "dpll" };
PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
+static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
+ RK2928_MODE_CON, 0, 5, rk3188_pll_rates),
+ [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
+ RK2928_MODE_CON, 4, 4, NULL),
+ [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
+ RK2928_MODE_CON, 8, 6, rk3188_pll_rates),
+ [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
+ RK2928_MODE_CON, 12, 7, rk3188_pll_rates),
+};
+
static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
@@ -737,8 +748,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)
static void __init rk3066a_clk_init(struct device_node *np)
{
rk3188_common_clk_init(np);
- rockchip_clk_register_plls(rk3188_pll_clks,
- ARRAY_SIZE(rk3188_pll_clks),
+ rockchip_clk_register_plls(rk3066_pll_clks,
+ ARRAY_SIZE(rk3066_pll_clks),
RK3066_GRF_SOC_STATUS);
rockchip_clk_register_branches(rk3066a_clk_branches,
ARRAY_SIZE(rk3066a_clk_branches));
--
2.1.1
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