Build reference: v3.18.3-98-g681eda0
Building arm:multi_v7_defconfig ... failed
--------------
Error log:
drivers/clk/rockchip/clk-rk3188.c:215:50: error: macro "PLL" passed 11 arguments, but takes just 10
RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
^
drivers/clk/rockchip/clk-rk3188.c:214:11: error: 'PLL' undeclared here (not in a function)
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
^
drivers/clk/rockchip/clk-rk3188.c:217:38: error: macro "PLL" passed 11 arguments, but takes just 10
RK2928_MODE_CON, 4, 4, 0, NULL),
^
drivers/clk/rockchip/clk-rk3188.c:219:71: error: macro "PLL" passed 11 arguments, but takes just 10
RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^
drivers/clk/rockchip/clk-rk3188.c:221:72: error: macro "PLL" passed 11 arguments, but takes just 10
RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^
make[3]: *** [drivers/clk/rockchip/clk-rk3188.o] Error 1
Caused by patch 'clk: rockchip: fix rk3066 pll lock bit location'.
Guenter
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