On Wed, Oct 19, 2022 at 12:19:49PM +0300, Ville Syrjälä wrote: > On Wed, Oct 19, 2022 at 12:00:02PM +0300, Jani Nikula wrote: > > On Tue, 18 Oct 2022, Imre Deak <imre.deak@xxxxxxxxx> wrote: > > > Accessing the TypeC DKL PHY registers during modeset-commit, > > > -verification, DP link-retraining and AUX power well toggling is racy > > > due to these code paths being concurrent and the PHY register bank > > > selection register (HIP_INDEX_REG) being shared between PHY instances > > > (aka TC ports) and the bank selection being not atomic wrt. the actual > > > PHY register access. > > > > > > Add the required locking around each PHY register bank selection-> > > > register access sequence. > > > > I honestly think the abstraction here is at a too low level. > > > > Too many places are doing DKL PHY register access to begin with. IMO the > > solution should be to abstract DKL PHY better, not to provide low level > > DKL PHY register accessors. > > > > Indeed, this level of granularity leads to a lot of unnecessary > > lock/unlock that could have a longer span otherwise, and the interface > > does not lend itself for that. > > It's no worse than uncore.lock. No one cares about that in > these codepaths either. > > > Also requires separate bank selection for > > every write, nearly doubling the MMIO writes. > > Drop in the ocean. This is all slow modeset stuff anyway. > > IMO separate reg accessors is the correct way to handle indexed > registers unless you have some very specific performance concerns > to deal with. Now, whether those accessors need to be visible everywere is another matter. It should certainly be possible to suck all dkl phy stuff into one file and keep the accessors static. But currently eveything is grouped by function (PLLs in one file, vswing stuff in another, etc.). We'd have to flip that around so that all the sub functions of of each IP block is in the same file. Is that a better apporach? Not sure. -- Ville Syrjälä Intel
