On Wed, Oct 19, 2022 at 12:00:02PM +0300, Jani Nikula wrote: > On Tue, 18 Oct 2022, Imre Deak <imre.deak@xxxxxxxxx> wrote: > > Accessing the TypeC DKL PHY registers during modeset-commit, > > -verification, DP link-retraining and AUX power well toggling is racy > > due to these code paths being concurrent and the PHY register bank > > selection register (HIP_INDEX_REG) being shared between PHY instances > > (aka TC ports) and the bank selection being not atomic wrt. the actual > > PHY register access. > > > > Add the required locking around each PHY register bank selection-> > > register access sequence. > > I honestly think the abstraction here is at a too low level. > > Too many places are doing DKL PHY register access to begin with. IMO the > solution should be to abstract DKL PHY better, not to provide low level > DKL PHY register accessors. > > Indeed, this level of granularity leads to a lot of unnecessary > lock/unlock that could have a longer span otherwise, and the interface > does not lend itself for that. It's no worse than uncore.lock. No one cares about that in these codepaths either. > Also requires separate bank selection for > every write, nearly doubling the MMIO writes. Drop in the ocean. This is all slow modeset stuff anyway. IMO separate reg accessors is the correct way to handle indexed registers unless you have some very specific performance concerns to deal with. > I think the choice of intel_tc.c is indicative of the problems in > abstraction. That file has zero DKL PHY register access currently, but > becomes the focal point of DKL PHY. > > I'd aim at adding intel_dkl_phy.c which is the only place that includes > intel_dkl_phy_regs.h and only place that directly uses the DKL PHY > registers. And with that, maybe you don't need to add any DKL PHY > specific register accessors. Ripping out the PHY specific junk from eg. intel_ddi.c I think would be a good goal. But that should also be done for the mg phy. -- Ville Syrjälä Intel
