On 7/20/2017 1:25 PM, David Miller wrote:
From: Allen Pais <allen.pais@xxxxxxxxxx>
Date: Thu, 20 Jul 2017 13:10:36 +0530
From: Vijay Kumar <vijay.ac.kumar@xxxxxxxxxx>
Added 5-Level paging for sparc.
Signed-off-by: Vijay Kumar <vijay.ac.kumar@xxxxxxxxxx>
Reviewed-by: Bob Picco <bob.picco@xxxxxxxxxx>
Signed-off-by: Allen Pais <allen.pais@xxxxxxxxxx>
So for one chip, we're going to unconditonally eat an entire
level of page table traversal on every PTE lookup?
Either stick to what 4-level page tables support for M8 or
make it run time selectable.
Thanks.
I will look into it. Thanks for your input.
Thanks,
Vijay
--
To unsubscribe from this list: send the line "unsubscribe sparclinux" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
