Re: Sun4c interrupt controller, MMU, IOMMU?

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Hi David,


All DMA is translated by the cpu's MMU as if it were a memory
reference made by the cpu itself.  Any missed DMA translation watchdog
resets the cpu.

I am getting a watchdog reset as soon as I enable interrupts after rebooting the kernel from SunOS or a prom_halt. Could in-proper DMA settings be the cause of this? After the watchdog reset or a powre-up reset, there is no problem booting Linux !.

Note: I am using SunOS4.1.1 boot so the kernel mappings for linux are
not what the loader is expecting.

SunOS does not have this problem but they hard code things so that they can get interrupts etc. up and running very much earlier on than Linux so it is very dificult to compare the sequence of events during boot for the two kernels.

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