Hi, I'm trying to add Sun4c (SS-2) support to Qemu. I'm using Linux source as the reference, but some things are not very clear. Specifically, how are the interrupts routed, which interrupts (ZS, ESP, Lance, timers, floppy, cgthree) go through the interrupt controller? How do the controller bits map to each interrupt source and PIL? Any docs for the controller, what is the device chip ID? I guess the MMU is similar in operation to Sun4u/v I/D TLB, is that correct? Any CPU docs would be helpful. There is no IOMMU, so the DMA is limited to lowest 16 megs, right? - To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
