Hi All,
I have been working on the SunMMU used by sun4c (SS1/SS2).
The attached file is work in progress so it may not be 100% correct. You
will need a wide screen (150 columns) to view the file.
I am using a SS1 Clone, a disassembler and verious bits of SunOS, Solaris
and Linux source code to validate it (and to work out why sun4c Linux is
so restrictive in what alterations can be made to the code without
breaking things completely).
The linux code for handling the cache is very similar to that used by
SunOS/Solaris (different register choices apers to be the only
difference).
The only low level code in this area that I might change in the future is
the sun4c_complete_all_stores() function in mm/sun4c.c. Reading the
context register and then executing 6 nop's should be sufficient, but
untill I have sorted out some more fundemental (and as yet un-explained)
stability issues I will will not be in a position to test this out
properly.
There is source code for Solaris 2.6 on the web. This is the best source
code reference you will get for sun4c as the low level code has not been
changed significantly from that of the architecture reference kernel
(SunOS 4.1 - see Sparc SCD 1.1).
The un-explained Linux features I am currently working on are:
1) 3MB Max size. SunOS remaps first 4MB. If Linux is changed to also remap
the first 4MB instead of just 3M it breaks.
2) Linux runs at VMA F0000000. SunOS runs at VMA F8000000. If Linux is
changed ro run at VMA F80000000 it breaks.
David/Anton may be able to explain these to me quickly :) but working
through the code slowly will probably teach me more about what is going
on.
If Anton and/or David have the time to brouse through my simple SunMMU
file and comment in it it might be helpfull.
Regards
Mark Fortescue.
On Sun, 12 Aug 2007, Blue Swirl wrote:
On 8/12/07, David Miller <davem@xxxxxxxxxxxxx> wrote:
Specifically, how are the interrupts routed, which interrupts (ZS,
ESP, Lance, timers, floppy, cgthree) go through the interrupt
controller?
There is no interrupt controller, the individual devices and
SBUS slot interrupt sources are wired up directly to the cpu.
Then what device is poked by arch/sparc/kernel/sun4c_irq.c, I thought
this was the controller?
Thanks for the other information. Implementing the MMU is going to be difficult.
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SunMMU:
There are two versions, a 2-Level Version and a 3 Level Version.
The 2-Level version is what is found on the sun4c.
Looking at Linux sparc32 head.S, the 3-Level implementation is found on Sun4/4xx and is described as Sun4-Mutant-MMU.
----------------------------------------------------------------------------------------------------------------------------------------
2-Level Sun4c Implementation:
Virtual Address: 1GB organised as 512MB (Low) + 512MB (High)
Physical Address: 256MB OBMEM + 256MB OBIO
32bit Virtual Address is the 30bit Virtual Address Sign Extended to 32bits.
The result is that there is a 3GB Hole in the middle of the 32bit Virtual Address space.
|--------------->------------------|
| |
Virtual Address | Physical Address |
________________________________ _______________________________
| SegmentNum | PTENum | Offset | | I/O | PageFrameNum | Offset |
|------------|--------|--------| |-----|--------------|--------|
29 18 17 12 11 0 31 28 27 12 11 0
| | | |
| | | |------------------------------------------<-----------------------------------------|
| | | |
| | |-------------------------------<--------------------------------| |
| | | |
| |------------------->---------------------| | |
| | |(I/O Sign Extended to 4bits) |
|---------->------------| | | |
| | | |
SMEIndex | SME* | | |
________________________ _____________ | | |
|-->--| Context | SegmentNum | -> | GROUP-NUM | | | |
| |---------|------------| |-----------| | | |
| c+11 12 11 0 7 0 | | |
| | | | |
| | | | |
Context | PTEIndex | | PTE | |
___________ _______________________________ _______________________________________________________________________
| Context | ---------->---------- | Context | GroupNum | PTENum | -> | VALID | PROT | NO-CACHE | TYPE | REF | MOD | resvd | PAGE-FRAME |
|---------| |---------|----------|--------| | | W | S | | 0 | I/O | | | | |
c | 0 c+g+5 g+6 g+5 6 5 0 |-------|---|---|----------|---|-----|-----|-----|-------|------------|
| 31 30 29 28 27 26 25 24 23 16 15 0
c=log2(NoContexts) g=log2(NoGroups)
VALID Page Valid Bit
PROT Access Protection
W Write Enable Bit
S System Page Bit
NO-CACHE No Cache Bit
TYPE Page Type
00 On Board Memory
01 On Board I/O
1x Undefined
REF Referenced Bit (Hardware)
MOD Modified Bit (Hardware)
resvd Reserved (Reads as Zero on SS1)
PAGE-FRAME Page Frame Number
PTE's are accessed at ASI_CTL[CONTEXT_REG] + ASI_PM[vaddr]
SME's are accessed at ASI_CTL[CONTEXT_REG] + ASI_SM[vaddr] *sun4c SME may be > 8bits but PROM V0 only uses GroupNum 0 to 127.
NoGroups : Read from Prom or use 128 (<= 4096)
NoContexts : Read from Prom or use 8
