Array BIST is a new type of core test introduced under the Intel Infield
Scan (IFS) suite of tests.
Emerald Rapids (EMR) is the first CPU to support Array BIST.
Array BIST performs tests on some portions of the core logic such as
caches and register files. These are different portions of the silicon
compared to the parts tested by the first test type
i.e Scan at Field (SAF).
Make changes in the device driver init flow to register this new test
type with the device driver framework. Each test will have its own
sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to
accommodate for the differences in test type and how they are initiated.
Upcoming patches will add actual support.
Signed-off-by: Jithu Joseph <jithu.joseph@xxxxxxxxx>
Reviewed-by: Tony Luck <tony.luck@xxxxxxxxx>
---
drivers/platform/x86/intel/ifs/ifs.h | 5 ++
drivers/platform/x86/intel/ifs/core.c | 70 ++++++++++++++++++---------
2 files changed, 52 insertions(+), 23 deletions(-)
diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h
index 046e39304fd5..2cef88a88aa9 100644
--- a/drivers/platform/x86/intel/ifs/ifs.h
+++ b/drivers/platform/x86/intel/ifs/ifs.h
@@ -137,6 +137,11 @@
#define SCAN_TEST_PASS 1
#define SCAN_TEST_FAIL 2
+enum test_types {
+ IFS_SAF,
+ IFS_ARRAY,
+};
+
/* MSR_SCAN_HASHES_STATUS bit fields */
union ifs_scan_hashes_status {
u64 data;
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index 206a617c2e02..ab234620ef4c 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,27 +16,44 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
-static struct ifs_device ifs_device = {
- .data = {
- .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+static struct ifs_device ifs_devices[] = {
+ [IFS_SAF] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
+ .test_num = IFS_SAF,
+ },
+ .misc = {
+ .name = "intel_ifs_0",
+ .nodename = "intel_ifs/0",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
- .misc = {
- .name = "intel_ifs_0",
- .nodename = "intel_ifs/0",
- .minor = MISC_DYNAMIC_MINOR,
+ [IFS_ARRAY] = {
+ .data = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_ARRAY,
+ },
+ .misc = {
+ .name = "intel_ifs_1",
+ .nodename = "intel_ifs/1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
+ int ndevices = 0;
u64 msrval;
- int ret;
+ int i;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -51,28 +68,35 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- ifs_device.misc.groups = ifs_get_groups();
-
- if (!(msrval & BIT(ifs_device.data.integrity_cap_bit)))
- return -ENODEV;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit)))
+ continue;
- ifs_device.data.pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
- if (!ifs_device.data.pkg_auth)
- return -ENOMEM;
+ ifs_devices[i].data.pkg_auth = kmalloc_array(topology_max_packages(),
+ sizeof(bool), GFP_KERNEL);
+ if (!ifs_devices[i].data.pkg_auth)
+ continue;
+ ifs_devices[i].misc.groups = ifs_get_groups();
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_device.data.pkg_auth);
- return ret;
+ if (misc_register(&ifs_devices[i].misc))
+ kfree(ifs_devices[i].data.pkg_auth);
+ else
+ ndevices++;
}
- return 0;
+ return ndevices ? 0 : -ENODEV;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_device.data.pkg_auth);
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device) {
+ misc_deregister(&ifs_devices[i].misc);
+ kfree(ifs_devices[i].data.pkg_auth);
+ }
+ }
}
module_init(ifs_init);
--
2.25.1
