Array BIST is a new type of core test introduced under the Intel Infield Scan (IFS) suite of tests. Emerald Rapids (EMR) is the first CPU to support Array BIST. Array BIST performs tests on some portions of the core logic such as caches and register files. These are different portions of the silicon compared to the parts tested by Scan at Field (SAF). Unlike SAF, Array BIST doesn't require any test content to be loaded. Jithu Joseph (5): x86/include/asm/msr-index.h: Add IFS Array test bits platform/x86/intel/ifs: Introduce Array Scan test to IFS platform/x86/intel/ifs: Sysfs interface for Array BIST platform/x86/intel/ifs: Implement Array BIST test platform/x86/intel/ifs: Trace support for array test arch/x86/include/asm/msr-index.h | 2 + drivers/platform/x86/intel/ifs/ifs.h | 18 ++++ include/trace/events/intel_ifs.h | 27 ++++++ drivers/platform/x86/intel/ifs/core.c | 82 ++++++++++++------ drivers/platform/x86/intel/ifs/runtest.c | 104 ++++++++++++++++++++++- drivers/platform/x86/intel/ifs/sysfs.c | 17 +++- 6 files changed, 223 insertions(+), 27 deletions(-) base-commit: 6d796c50f84ca79f1722bb131799e5a5710c4700 -- 2.25.1
