2013/2/27 sandeep kumar <coolsandyforyou@xxxxxxxxx>
>"volatile" only say to the compiler to not put the variable in a register.>Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine?In development phase of the board, we are trying to measure RAM performance gain while changing type of the RAM.The standard benchmark tools are giving us the Cache performance only. So we want to try some method to measure RAM performance.
ok.
The answear is hardware-dependent, some hardware may have a way to disable the cachability (but will probly need to be in the kernel).
But to skeep the hardware dependencie, you need to read a part of memory that is not cached.
The best way is to do the test at boot time when the caches are cold. I dont think that a user-space application could do this in precise way, since it cannot know the physical address it address....
Doing a small "boot" code and booted directly (without grub) could give some precise numbers.
You will also need to space yout read request (128*8 byte for example), since most cache caches a line while you have read only one word.
Hope i helped.
regards.
On Wed, Feb 27, 2013 at 2:30 PM, Karaoui mohamed lamine <moharaka@xxxxxxxxx> wrote:
2013/2/27 sandeep kumar <coolsandyforyou@xxxxxxxxx>
>>I am not sure but what if you make the variable as a volatile?Hey i tried. But still is showing the same time for int & volatile int."volatile" only say to the compiler to not put the variable in a register.Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine?ThanksSandeep
On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi <ankurengg2003@xxxxxxxxx> wrote:
I am not sure but what if you make the variable as a volatile?On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar <coolsandyforyou@xxxxxxxxx> wrote:
Hi AllIn performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only.I want to measure my DDR(RAM chip) performance.So i want to make sure, every read/write should happen to DDR RAM chip only.How can i achieve this...Any ideas/suggestions...?--
With regards,
Sandeep Kumar Anantapalli,
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Thanks
Ankur Dwivedi
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With regards,
Sandeep Kumar Anantapalli,
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With regards,
Sandeep Kumar Anantapalli,
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