>let' see....
>what if you do read and write pattern, in certain order so that it
>will be invalidated by the L1/L2/L3 cache everytime?
And how do you suggest we do that?? That is infact my question..
>what if you do read and write pattern, in certain order so that it
>will be invalidated by the L1/L2/L3 cache everytime?
And how do you suggest we do that?? That is infact my question..
On Tue, Feb 26, 2013 at 9:05 PM, Mulyadi Santosa <mulyadi.santosa@xxxxxxxxx> wrote:
On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumarlet' see....
<coolsandyforyou@xxxxxxxxx> wrote:
> Hi All
> In performance benchmark tools, When we profile read/write timings mostly,
> those read/writes are done to cache only.
>
> I want to measure my DDR(RAM chip) performance.
> So i want to make sure, every read/write should happen to DDR RAM chip only.
what if you do read and write pattern, in certain order so that it
will be invalidated by the L1/L2/L3 cache everytime?
AFAIK, one thing for sure, reading data from sequentially and re-read
them will make end up reading cache in the 2nd operation and so on.
I think the most certain way to do it is to read data (or write) data
bigger than total L1/L2/L3 cache.
--
regards,
Mulyadi Santosa
Freelance Linux trainer and consultant
blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com
With regards,
Sandeep Kumar Anantapalli,
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