But How this will work in ARM/x86 we don't have such address space division, is that done by pagetable settings? Nobin On Thu, Apr 1, 2010 at 10:37 PM, Nobin Mathew <nobin.mathew@xxxxxxxxx> wrote: > I got a link for MIPS > http://www.johnloomis.org/microchip/pic32/memory/memory.html > > > On Thu, Apr 1, 2010 at 10:32 PM, Nobin Mathew <nobin.mathew@xxxxxxxxx> wrote: >> How we will make the uncached region, is this a hardware facility? or >> Paging facility, marking pages as uncacheable? >> >> what is KSEG1 register in MIPS? >> >> On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody@xxxxxxxxx> wrote: >>> hi: >>> >>> 2010/4/1 Nobin Mathew <nobin.mathew@xxxxxxxxx>: >>>> I have a basic question regarding caching >>>> >>>> 1) Will peripheral device registers be cached in cache memory? >>> if your register locate the place where cpu don't cache it. >>> it won't be cached. >>> take mips for example, address after 0xa0000000 is uncache and if your >>> registers are located there, it won't be cached. >>> >>>> 2) If not how caching is avoided for this address? >>> flush it back after you finish setting all the registers. >>> >>>> 3) If yes how is asynchronous changes in hardware registers is getting >>>> reflected in value read from that register. >>>> #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned >>>> char __force *)(a)) >>>> #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned >>>> char __force *)(a) = (v)) >>>> >>>> will volatile does that magic? I don't think so. Please correct me if >>>> I am wrong. >>> As far as I know, volatile is used to force compiler not to do the optimism. >>> and cache is the behaviour of your cpu. >>> >>> Hope this help, >>> miloody >>> >>>> >>>> Thanks in Advance >>>> >>>> Nobin >>>> >>>> -- >>>> To unsubscribe from this list: send an email with >>>> "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx >>>> Please read the FAQ at http://kernelnewbies.org/FAQ >>>> >>>> >>> >> > -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
