On Thu, Apr 1, 2010 at 11:06 AM, Nobin Mathew <nobin.mathew@xxxxxxxxx> wrote:
I have a basic question regarding caching
1) Will peripheral device registers be cached in cache memory?
2) If not how caching is avoided for this address?
3) If yes how is asynchronous changes in hardware registers is getting
reflected in value read from that register.
#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned
char __force *)(a))
#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned
char __force *)(a) = (v))
Device register address should never be cached. In case of MIPS architecture device registers are mapped onto uncached address space.
I am sure other architecture must be providing similar kind of provision.
I am sure other architecture must be providing similar kind of provision.
will volatile does that magic? I don't think so. Please correct me if
I am wrong.
Thanks in Advance
Nobin
~cnanda
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