On Wed, 24 May 2006, Erik Scharwaechter wrote:
I seem to recall reading somewhere that the interrupt input on x86 CPU's
are edge sensitive rather than level sensitive, which throws the above
...
Indeed, I assumed the INTR interrupt input line to be edge-sensitive.
Using Google, I found out the following:
...
recognized later, even if they are negated before being recognized. The
four level-sensitive interrupts (BUSCHK#, R/S#, INTR, and STPCLK#) must be
...
So it seems that INTR on the CPU is level sensitive. However, there is
always some sort of interrupt controller between an external device and
the CPU (originally, one or two 8259 chips) which also has its say in
how things are handled.
Does anyone on the list know offhand how the interrupt controller affects
the interrupt signal logic?
/Ricard
--
Ricard Wolf Wanderlöf ricardw(at)axis.com
Axis Communications AB, Lund, Sweden www.axis.com
Phone +46 46 272 2016 Fax +46 46 13 61 30
