On Wed, May 24, 2006 at 04:52:21PM +0530, Gaurav Dhiman wrote: > When IF flag is set to 0, IPC do send the interrupt signals to CPU on > INTR pin but CPU simply do not honour them. Unless and untill CPU does > not honour and acknowledge back the interrupt to IPC, IPC does keep > note of interrupt as pending. When IF flag is set to 1 again, then > these pending interrupts are handled. I see, so the PIC seems to have a tracking mechanism similar to the queue I proposed. Now, I'm wondering how the PIC notices that the IF flag is reset to 1 again. Is it done with a trial-and-error method by sending these pending interrupts over and over again until they have been honoured by the CPU? Or is there an additional line between the PIC and the CPU to indicate the state of this flag? > Read more on this: > http://lkdp.blogspot.com/2006/01/interrupt-handling-internals-in-linux_22.html Thank you for the link! Regards, Erik -- Erik Scharwaechter http://diozaka.org GPG: 0x42B654AB -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
