On Wed, May 24, 2006 at 05:01:53PM +0200, Ricard Wanderlof wrote: > Thus the device does not 'resend the interrupt', rather it keeps its > interrupt line activated until told to release it. > [...] > Thus, an interrupt cannot be lost by the CPU disabling its interrupt > flag; it will simply occur when interrupts are later enabled. Thank you for clarifying this! > I seem to recall reading somewhere that the interrupt input on x86 CPU's > are edge sensitive rather than level sensitive, which throws the above > reasoning off a bit (and makes low level interrupt programming awkward at > best). Indeed, I assumed the INTR interrupt input line to be edge-sensitive. Using Google, I found out the following: "The four edge-triggered interrupts (FLUSH#, SMI#, INIT, and NMI) are latched on one of the edges of CLK when they are asserted and are recognized later, even if they are negated before being recognized. The four level-sensitive interrupts (BUSCHK#, R/S#, INTR, and STPCLK#) must be held asserted until recognized, except that the BUSCHK# interrupt is sampled and latched with every BRDY#." (http://www.warthman.com/ex-int.htm) > I'd be happy if anyone could shed any light on this, although we are > getting far from the kernel and dangerously close to the bare metal here. Well, I hope this is not a problem, as this topic is really highly interesting. Regards, Erik -- Erik Scharwaechter http://diozaka.org GPG: 0x42B654AB -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
