Hi Yang!
Yang Huang wrote:
Morning Manav,
I tried to define L1_CACHE_BYTES to 0, and cannot compile the kernel.
error message tells:
include/asm/processor.h:68: error: requested alignment is not a power of 2
I dig a bit into the source and guess SMP_CACHE_BYTES (in
asm/processor.h)has sth to do with the L1_CACHE_BYTES, and does not
allow its value to be zero.
Then I tried to make it 2 (not very smart trick...), compilation still
failed, with report below:
include/net/sock.h:565: error: size of array '__pad' is too large
I also compiled the kernel, setting msr as a module, without touching
the L1_CACHE_BYTES. And then insert msr.ko after Linux is loaded,
according to major number suggested in devices.txt (major : 202), I
mknod a msr device as well. It seems that I can open, read, and write
msr successfully (well, at least perror tells "Success"), but what I
read is 0x0, and writing to the device does not make any sence!
That was a good effort!
include/net/sock.h:565: error: size of array '__pad' is too large
It is true that messing up with L1_CACHE_BYTES breaks networking in some
cases. Kindly look at,
http://www.alphalinux.org/archives/linux-alpha/August2000/0000.html
for an example, which I found this on the web. It seems to work fine on
SMP though.
I know this would be a very interesting task, and I really want to
know how to solve this problem. As a newbie in the newbies' list, I
will appreciate very much your help!
I am a newbie myself and hence subscribed to Kernel Newbies! ;-)
I am in the office at the moment and a bit loaded with work - my PPI
driver is finally coming to shape now..
I will look into this in my free time, and let you know as soon as I get
something useful.
Best Regards,
Manav
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