Morning Manav, I tried to define L1_CACHE_BYTES to 0, and cannot compile the kernel. error message tells: include/asm/processor.h:68: error: requested alignment is not a power of 2 I dig a bit into the source and guess SMP_CACHE_BYTES (in asm/processor.h)has sth to do with the L1_CACHE_BYTES, and does not allow its value to be zero. Then I tried to make it 2 (not very smart trick...), compilation still failed, with report below: include/net/sock.h:565: error: size of array '__pad' is too large I also compiled the kernel, setting msr as a module, without touching the L1_CACHE_BYTES. And then insert msr.ko after Linux is loaded, according to major number suggested in devices.txt (major : 202), I mknod a msr device as well. It seems that I can open, read, and write msr successfully (well, at least perror tells "Success"), but what I read is 0x0, and writing to the device does not make any sence! I know this would be a very interesting task, and I really want to know how to solve this problem. As a newbie in the newbies' list, I will appreciate very much your help! Best regards, Yang -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
