Hi list,
In previous mail discussing how to disable the CPU cache, I got
another question, which I guess it would be better to make a new
thread.
I search for a while, but without satisfied answer. As for CR0, the
Machine State Word Register, almost all documents give the following
info:
|31|30-5|4|3|2|1|0| Machine Status Word
| | | | | | +---- Protection Enable (PE)
| | | | | +----- Math Present (MP)
| | | | +------ Emulation (EM)
| | | +------- Task Switched (TS)
| | +-------- Extension Type (ET)
| +---------- Reserved
+------------- Paging (PG)
Then here comes my question: what is bit 5 to bit 30 here? What I know
up to now is if bit 30 is set, the cache of CPU is disabled (whether
L1 or L2 is unknow yet). Then what about others?
Could any body shed some light on this?
TIA
Yang
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