On Sat, Sep 18, 2004 at 12:36:19AM +0530, Dhiman, Gaurav wrote: > Take an example of IRQ 0 (PIC 1 , pin 0), for this PIC 1 will send 0x08 > to CPU (as I read it from an online article on PIC Details : > http://www.beyondlogic.org/interrupts/interupt.htm), which does not > represents the vector number 0x20 in IDT for IRQ 0. Similarly if we take > an example of any interrupt on PIC 2, lets take an example of IRQ 8 (PIC > 2, pin 0), PIC 2 will send 0x70 to CPU which is not the vector number > for IRQ 7 (vector number of IRQ 7 should be 0x28, if I am right). In the example above the interrupt vector offsets are initialized to different values (0x08 and 0x70) than in the linux kernel (0x20 and 0x28). It is also irrelevant. You don't have to know anything about the PICs to know that the CPU will simply take the value it reads from the bus during the interrupt request to determine the offset into the IDT, because that's the way it is specified. > Can you also let me know one more thing, how can we refer to single PIC > register with different roles. For example, we sometimes take 0x20 and > 0xA0 status registers to be Interrupt Request Register (IRR) and some > time we consider them to be Interrupt Status Register (ISR). [...] It's wrong to think of these ports as register addresses. They are simply I/O adresses assigned to the 8259A PICs. During initialization so-called Initialization Command Words (ICWs) are written to theses addresses. The meaning of the command words is determined by their sequence. Note that I knew nothing about the 8259A before answering your questions. I found the answers to your questions simply by reading documentation. Wild speculation will get you nowhere. Clemens -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
