Hi Clemens, Thanks for giving me hint, but I am still not satisfied with your response. I saw the code in init_8259A() function, the code is as follows: outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ if (auto_eoi) outb_p(0x03, 0x21); /* master does Auto EOI */ else outb_p(0x01, 0x21); /* master expects normal EOI */ outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode is to be investigated) */ Ok, fine as you said that we set interrupt vector offsets to 0x20 and 0x28 for PIC1 and PIC2 respectively, yes it there in this code, but I am not able to understand that what is the use of setting these vector offset in PIC when PIC is not making use of it while sending the bit string (IDT vector number) to CPU, because what PIC is sending to CPU is something different, that does not represent the vector number. Take an example of IRQ 0 (PIC 1 , pin 0), for this PIC 1 will send 0x08 to CPU (as I read it from an online article on PIC Details : http://www.beyondlogic.org/interrupts/interupt.htm), which does not represents the vector number 0x20 in IDT for IRQ 0. Similarly if we take an example of any interrupt on PIC 2, lets take an example of IRQ 8 (PIC 2, pin 0), PIC 2 will send 0x70 to CPU which is not the vector number for IRQ 7 (vector number of IRQ 7 should be 0x28, if I am right). Can you also let me know one more thing, how can we refer to single PIC register with different roles. For example, we sometimes take 0x20 and 0xA0 status registers to be Interrupt Request Register (IRR) and some time we consider them to be Interrupt Status Register (ISR). Taking an example of above code only, we are writing 0x21 register for initializing the vector offset in PIC, but actually 0x21 is a mask register as well, so if we are executing the following instruction to initialize the vector offset, are we not disabling (or masking) IRQ 3 on PIC 1, as this register also works as mask register. outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ Regards, Gaurav -----Original Message----- From: Clemens Buchacher [mailto:drizzd@xxxxxx] Sent: Saturday, September 18, 2004 11:38 PM To: Dhiman, Gaurav Cc: Vinod Sreedharan; kernelnewbies@xxxxxxxxxxxx Subject: Re: Low Level Interrupt Handling On Fri, Sep 17, 2004 at 05:37:39PM +0530, Dhiman, Gaurav wrote: > [...] if interrupts occur on pin 3 of PIC 1 (IRQ 3) [...], then the > bit string the CPU will receive will be "00001011". Similarly if > interrupt occurs on any pin of PIC 2, then the format will be "01110<3 > bits representing the pin number on PIC 2>", so if interrupt occurs on > pin 3 of PIC2 (IRQ 10), then the CPU will receive the "01110011" bit > string. No, the interrupt vector offsets are initialized to 0x20 and 0x28 for PIC1 and PIC2, respectively, in init_8259A. The CPU does not `interpret' the vector number received from the PICs in any way. -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
