Re: Low Level Interrupt Handling

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On Fri, Sep 17, 2004 at 05:37:39PM +0530, Dhiman, Gaurav wrote:
> [...] if interrupts occur on pin 3 of PIC 1 (IRQ 3) [...], then the
> bit string the CPU will receive will be "00001011". Similarly if
> interrupt occurs on any pin of PIC 2, then the format will be "01110<3
> bits representing the pin number on PIC 2>", so if interrupt occurs on
> pin 3 of PIC2 (IRQ 10), then the CPU will receive the "01110011" bit
> string.

No, the interrupt vector offsets are initialized to 0x20 and 0x28 for
PIC1 and PIC2, respectively, in init_8259A. The CPU does not `interpret'
the vector number received from the PICs in any way.

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