hi all, the problem's solved! it was due a stupid oversight by me...... :) the following will exit the moment the reset bit i.e bit 5 becomes 0: ResetCmd = 0x10 while(readb(ChipCmdReg) & ResetCmd); thanx all, - /dev/mandeep -----Original Message----- From: Jan Hudec [mailto:bulb@ucw.cz] Sent: Thursday, April 01, 2004 3:32 PM To: Mandeep Singh Sandhu Cc: kernelnewbies@nl.linux.org Subject: Re: I/O caching prob On Thu, Apr 01, 2004 at 10:07:35 +0530, Mandeep Singh Sandhu wrote: > hi all, > > i'm facing a problem while reseting a chip. > to reset the chip (RTL8139) i write a byte into it's > command reg. and wait for the a bit to be 0 which > indicates that the reset is complete. > > to test this bit i had first written a tight while loop > as follows > > while((readb(ChipCmdReg) & ResetCmd) == 0); Didn't you say you are waiting for it to become ZERO? This loop waits for it to become NON-zero. > but the comp used to hang when it used reach this loop. > it never came out. > > then i wrote: > i = 1000; > while(i) > if((readb(ChipCmdReg) & ResetCmd) == 0) > break; > else > i--; > > this worked! And on which condition did it exit? That's quite important, don't you think? ------------------------------------------------------------------------ ------- Jan 'Bulb' Hudec <bulb@ucw.cz> -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
