thanx velco, that cleared a lot of things. one last doubt hopefully... :) if i'm using an intel machine then can i use memory mapped I/O to communicate with my PCI device (use ioremap etc.), even though intel arch's use I/O mapped I/O???? In the ethernet driver for the realtek NIC 8139too.c a "#ifdef USE_IO_OPS" is used to choose between PCI I/O or Memory mapped I/O, where is this "USE_IO_OPS" defined and on what basis??? TIA, - /dev/mandeep -----Original Message----- From: Momchil Velikov [mailto:velco@fadata.bg] Sent: Tuesday, March 09, 2004 3:00 PM To: Mandeep Singh Sandhu Cc: kernelnewbies@nl.linux.org Subject: Re: what is the diff between PCI I/O & memory space >>>>> "Mandeep" == Mandeep Singh Sandhu <mandeep_sandhu@infosys.com> writes: Mandeep> few basic PCI doubts :- All doubts are usually cleared by reading the PCI spec. Mandeep> 1) What is difference between PCI I/O & Memory regions?? The PCI bus has several separate address spaces, accessed by issuing different PCI bus commands, i.e. driving C/BE[0:3]# lanes with the command code during the address phase of a PCI bus transaction. I/O and Memory space are simply two of these address spaces. On IA-32 usually inb/inw/ind/outb/outw/outd insns generate I/O Read/Write cycles, whereas ordinary memory load/store insns generate Memory Read/Write cycles. A device may request either I/O or Memory address or both to be allocated to it. There's no particular difference between the address spaces from the device point of view. Mandeep> 2) What r these 2 regions required for?? To communicate with the device, of course. Mandeep> 3) Linux's PCI subsystem provides some functions like Mandeep> "pci_resource_start" to get resource info. Mandeep> There's an arg passed to it - "int bar"(base adr. reg.). Mandeep> In one of the driver files i've seen for getting the I/O Mandeep> and Memory start addresses "bar" was passed as 0 & 1 Mandeep> respectively. In rubini's book it says these values can Mandeep> vary from 0 to 5 (for the 6 base addr. regs i guess!). Mandeep> what does these values signify. Does it mean BAR0 holds Mandeep> the start address of PCI I/O space etc.??? The PCI Configuration Space (note that this is yet another bus address space) contains six Base Address Registers, which are used by the devices to state its address requirements and later to obtain the device configuration. A BAR can specify either a I/O or Memory space. An I/O space BAR has the following format: aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa01 where a*30 is the address, bit 1 is reserved and zero, bit 0 is set 1 to indicate I/O space. A Memory space BAR has the following format: aaaaaaaaaaaaaaaaaaaaaaaaaaaaptt0 where a*28 is the address, p is prefetchable bit: 1-prefetchable, 0 non-prefetchable, tt are type bits: 00 - locate anywhere in 32-bit address space 01 - locate below 1M 10 - locate anywhere in 64-bit address space 11 - reserved ~velco -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
