Momchil Velikov wrote: > Yep. 88100/25Mhz and 88110/50Mhz on a MVME :) wow! 25-50Mhz? i wasn't aware it has been so long ago > The other end of the spectrum are rather VLIW CPUs, e.g. TI TMS320C6xxx > series. The "weird" thing (which I like _very_ much :) is that there's > no pipeline interlock, so if you have (not a C6x assembly): that's exactly what i meant; didn't the 88K had an execution mode to work this way? it wasn't VLIW, but i'm pretty sure i read about that on a motorola article i do find it weird, but at the time i thought it was brilliant. aparently not many uP engineers agree with us these days! > MTAs switch to the next insn stream every clock. _every_ clock? or just to avoid memory/cache stalls? > There are 128 HW threads, each having its own set of registers, > instruction pointer, etc. sounds like a lot... but i think registers are cheap these days. even the P4 has 128 internal registers to do renaming on just 8 visible registers we're getting OT now... i think the original questions about being it worthwhile to wait for a new P4 with HT are clear as mud, with a "definite maybe" conclusion. ----- Javier -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
