On Tue, 29 Oct 2002 17:18:06 -0500 Javier Guerra <listasJGG@eos.com.pe> wrote: > the other end of the spectrum was the Motorola 88000... have seen that > one? Yep. 88100/25Mhz and 88110/50Mhz on a MVME :) > a very weird ISA, where you (or the compiler) have to keep in > mind exactly what instructions are in what phase of the pipeline. Weird?! I still think this is the best ISA out there and one of the smallest too. IIRC the CPU had pipeline interlocks, so it was no different to other RISC CPUs. The other end of the spectrum are rather VLIW CPUs, e.g. TI TMS320C6xxx series. The "weird" thing (which I like _very_ much :) is that there's no pipeline interlock, so if you have (not a C6x assembly): ld r5, addr add r6, r5, 1 and the load is defined to have 2 cycles latency, the addition adds _the old_ value of r5, which may be exactly what one wants. If not, the compiler has to explicitly place nops like: ld r5, addr nop add r6, r6, 1 This is RISC philosophy to the max - let the compiler take care of the details and keep the IC simple, the die smaller, etc. > > Yep. Besides HT-aware thread scheduler, there's a need for HT-aware > > load balancing of interrupts, too, so you don't end up serving all > > the interrupts on one physical CPU. > > again, that might make HT counterproductive if it's not done ok by the > OS > > i don't know well how the cray MTA works; i think it's more like MTAs switch to the next insn stream every clock. > process scheduling, switching contexts inside the CPU, instead of > giving each instruction its own context (like the P4 does). There are 128 HW threads, each having its own set of registers, instruction pointer, etc. ~velco -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
