Momchil Velikov wrote: > You don't have *more* horsepower, you just *utilize* it more. yep, that's the main goal of most subunits inside modern processors > > the main bottleneck right now on the x86 architecture is getting such > > an old instruction set work nice with a superscalar processor. since > > Nope. The "old instruction" set disappears in pretty early state in the > pipeline(s). From that point on Intel CPUs are like everyone else's > RISC CPU. those magical 'internal risc-like instructions' help a lot; but the most interesting optimizations are done by the compiler... with old x86 instructions. > > it's so dificult for the OOOD unit to find enough non-exclusive > > instructions to fill the queues, it makes sense to pick instructions > > from two separate execution threads. > > This is true indeed for all CPU architectures out there, which is not a > surprise as it has nothing to do with CPU architecture, but rather with > compilers architecture and the way people write programs. absolutely right, but since the compilers still deal with x86 instructions, with very few (visible) registers, and (even worse) many instructions can only use this or that register for that function... all this makes very difficult to find instructions that can be dispatched simultaneously or out of order. the other end of the spectrum was the Motorola 88000... have seen that one? a very weird ISA, where you (or the compiler) have to keep in mind exactly what instructions are in what phase of the pipeline. > Yep. Besides HT-aware thread scheduler, there's a need for HT-aware > load balancing of interrupts, too, so you don't end up serving all the > interrupts on one physical CPU. again, that might make HT counterproductive if it's not done ok by the OS i don't know well how the cray MTA works; i think it's more like process scheduling, switching contexts inside the CPU, instead of giving each instruction its own context (like the P4 does). without more details, that sounds like a simpler, more conservative approach; but it wouldn't help fight the pipeline bubbles. OTOH, on a supercomputing architecture, one would think their processors aren't so 'bubbly' as intel's.... ----- Javier -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
