On 8/6/2018 11:19 PM, Rob Herring wrote:
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu <songjun.wu@xxxxxxxxxxxxxxx> wrote:From: Yixin Zhu <yixin.zhu@xxxxxxxxxxxxxxx> This driver provides PLL clock registration as well as various clock branches, e.g. MUX clock, gate clock, divider clock and so on. PLLs that provide clock to DDR, CPU and peripherals are shown below: +---------+ |--->| LCPLL3 0|--PCIe clk--> XO | +---------+ +-----------| | +---------+ | | 3|--PAE clk--> |--->| PLL0B 2|--GSWIP clk--> | | 1|--DDR clk-->DDR PHY clk--> | | 0|--CPU1 clk--+ +-----+ | +---------+ |--->0 | | | MUX |--CPU clk--> | +---------+ |--->1 | | | 0|--CPU0 clk--+ +-----+ |--->| PLLOA 1|--SSX4 clk--> | 2|--NGI clk--> | 3|--CBM clk--> +---------+ Signed-off-by: Yixin Zhu <yixin.zhu@xxxxxxxxxxxxxxx> Signed-off-by: Songjun Wu <songjun.wu@xxxxxxxxxxxxxxx> --- Changes in v2: - Rewrite clock driver, add platform clock description details in clock driver. drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 3 + drivers/clk/intel/Kconfig | 20 ++ drivers/clk/intel/Makefile | 7 + drivers/clk/intel/clk-cgu-pll.c | 166 ++++++++++ drivers/clk/intel/clk-cgu-pll.h | 34 ++ drivers/clk/intel/clk-cgu.c | 470 +++++++++++++++++++++++++++ drivers/clk/intel/clk-cgu.h | 259 +++++++++++++++ drivers/clk/intel/clk-grx500.c | 168 ++++++++++ include/dt-bindings/clock/intel,grx500-clk.h | 69 ++++This belongs with the clk binding patch. Rob
Thanks for review. Will move it to clock binding patch.
