On Fri, 29 Sep 2017, James Hogan wrote: > > NB if this turns out indeed used, then we might have to do something > > about DMFC0 hazard avoidance for the sake of MIPS III support, and also > > choose to use an MFC0/MFHC0 instruction pair instead on MIPS64r5+. > > This would have to depend on MVH bit, but in practice I suspect it isn't > worthwhile doing it here instead of in a separate macro to use depending > on the register. Boot-time patching would be more appropriate IMO. > Using MVH would have the advantage of avoiding the potential window when > a 32-bit EJTAG or Cache error handler potentially canonicalises register > state I suppose. > > That's another advantage of this patch actually, it reduces the size of > that window to a single instruction. That still sounds scary and justifies the use of MFHC0 (and MTHC0 in `__write_64bit_c0_split') where available more than just the minuscule performance improvement. Thanks for your review. Maciej
