On Tue, 2 Jun 2015, Joshua Kinard wrote:
> I commented on it being odd because out of four CPUs, #2 was coming up with a
> sign-extended value, twice (I tested two reboot cycles, same both times). I'm
> not fully knowledgable of IP27 hardware, and am probably one of the few on the
> planet in possession of R14K node boards, so this might be a quirk of these
> specific nodes. Would need others to test to verify, I guess.
That's how the CFC1 instruction works, it sign-extends the 32-bit value
written to the destination register on 64-bit processors. So if the chip
has come out of reset with FCSR.FCC[7] set, then the bit will be repeated
across bits 63:32 when the bit pattern from FCSR has been transferred to a
general-purpose register.
> As for a typo, nope:
>
> __enable_fpu(FPU_AS_IS);
>
> fcsr = read_32bit_cp1_register(CP1_STATUS);
> -> pr_info("CPU%d: FCSR is: %08lx\n", smp_processor_id(), fcsr);
> fcsr &= ~mask;
OK, thanks for confirming. So it looks like the cause of the exception
vanished at the same time. There's no harm in reinitialising FCSR here
though, any vendor-specific bits possibly set will be cleared on process
creation anyway.
Maciej
