[PATCH 3/3] MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

["Maciej W. Rozycki" <macro@xxxxxxxxxxxxxx>]

Replace an explicit barrier with a useful processor instruction in TLB 
invalidation, following several other such cases elsewhere in 
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxxxxx>
---
linux-mips-tlb-r3k-flush-barrier.diff
Index: linux-20150524-3maxp/arch/mips/mm/tlb-r3k.c
===================================================================
--- linux-20150524-3maxp.orig/arch/mips/mm/tlb-r3k.c
+++ linux-20150524-3maxp/arch/mips/mm/tlb-r3k.c
@@ -45,10 +45,10 @@ static void local_flush_tlb_from(int ent
 
 	old_ctx = read_c0_entryhi() & ASID_MASK;
 	write_c0_entrylo0(0);
-	for (; entry < current_cpu_data.tlbsize; entry++) {
+	while (entry < current_cpu_data.tlbsize) {
 		write_c0_index(entry << 8);
 		write_c0_entryhi((entry | 0x80000) << 12);
-		BARRIER;
+		entry++;				/* BARRIER */
 		tlb_write_indexed();
 	}
 	write_c0_entryhi(old_ctx);