Move the initialisation of the CP0.Wired register implemented by Toshiba
TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where
it belongs, correcting code structure and making sure initialisation
does not rely on `tx39_cache_init' being called before `tlb_init' to
work correctly.
Make `r3k_have_wired_reg' static as it's no longer externally referred
to; remove a stale declaration too.
Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxxxxx>
---
James,
You may have to reexport `r3k_have_wired_reg' if you implement R3k
SysRq-x changes I suggested and this change goes in first. In that case
I suggest that you put the declaration in a header, having them
scattered across .c files is asking for trouble.
Maciej
linux-mips-tlb-r3k-init-wired.diff
Index: linux-20150524-3maxp/arch/mips/lib/r3k_dump_tlb.c
===================================================================
--- linux-20150524-3maxp.orig/arch/mips/lib/r3k_dump_tlb.c
+++ linux-20150524-3maxp/arch/mips/lib/r3k_dump_tlb.c
@@ -14,8 +14,6 @@
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>
-extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
-
static void dump_tlb(int first, int last)
{
int i;
Index: linux-20150524-3maxp/arch/mips/mm/c-tx39.c
===================================================================
--- linux-20150524-3maxp.orig/arch/mips/mm/c-tx39.c
+++ linux-20150524-3maxp/arch/mips/mm/c-tx39.c
@@ -28,8 +28,6 @@ static unsigned long icache_size, dcache
#include <asm/r4kcache.h>
-extern int r3k_have_wired_reg; /* in r3k-tlb.c */
-
/* This sequence is required to ensure icache is disabled immediately */
#define TX39_STOP_STREAMING() \
__asm__ __volatile__( \
@@ -383,8 +381,6 @@ void tx39_cache_init(void)
case CPU_TX3927:
default:
/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
- r3k_have_wired_reg = 1;
- write_c0_wired(0); /* set 8 on reset... */
/* board-dependent init code may set WBON */
__flush_cache_vmap = tx39__flush_cache_vmap;
Index: linux-20150524-3maxp/arch/mips/mm/tlb-r3k.c
===================================================================
--- linux-20150524-3maxp.orig/arch/mips/mm/tlb-r3k.c
+++ linux-20150524-3maxp/arch/mips/mm/tlb-r3k.c
@@ -36,7 +36,7 @@ extern void build_tlb_refill_handler(voi
"nop\n\t" \
".set pop\n\t")
-int r3k_have_wired_reg; /* should be in cpu_data? */
+static int r3k_have_wired_reg; /* Should be in cpu_data? */
/* TLB operations. */
static void local_flush_tlb_from(int entry)
@@ -280,6 +280,13 @@ void add_wired_entry(unsigned long entry
void tlb_init(void)
{
+ switch (current_cpu_type()) {
+ case CPU_TX3922:
+ case CPU_TX3927:
+ r3k_have_wired_reg = 1;
+ write_c0_wired(0); /* Set to 8 on reset... */
+ break;
+ }
local_flush_tlb_from(0);
build_tlb_refill_handler();
}
