Hi Ralf, On 15/05/15 16:08, Ralf Baechle wrote: > On Wed, May 13, 2015 at 11:50:48AM +0100, James Hogan wrote: > >> Add hazard macros to <asm/hazards.h> for the following hazards around >> tlbr (TLB read) instructions, which are used in TLB dumping code and >> some KVM TLB management code: >> >> - mtc0_tlbr_hazard >> Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in >> all cases on the assumption that tlbr always has similar data user >> timings to tlbw. >> >> - tlb_read_hazard >> Between tlbr and mfc0 (various TLB registers). This is copied from >> tlbw_use_hazard in all cases on the assumption that tlbr has similar >> data writer characteristics to tlbw, and mfc0 has similar data user >> characteristics to loads and stores. >> >> Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx> >> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> >> Cc: linux-mips@xxxxxxxxxxxxxx >> --- >> Looking at r4000 manual, its tlbr had similar data user timings to tlbw, >> and mfc0 had similar data writer timings to loads and stores. Are there >> particular other cores that should be checked too? > > The R4600 and R5000 CPUs are important. The R4600 also covers the > R4700 and the R5000 the R52xx embedded cores. > > For most cases the R4000/R4400 due to their long pipeline represent the > worst case but there are exceptions. Okay. For mtc0-tlbw/tlbr on r4000: mtc0 CPR written stage 7 tlbwi/r CPR read stage 5-8 (5-7 for tlbr) delay = 7-5-1 = 1 nop but linux has 2 nops for __mtc0_tlbw_hazard. Is that one of the exceptions? ( For r4600, mtc0-tlbw/tlbr = 4-2-1 = 1 nop too For tlbr-mfc0, r4000: tlbr CPR written stage 8 mfc0 CPR read state 4 delay = 8-4-1 = 3 nops (that's what I have) r4600: tlbr CPR written stage 4 mfc0 CPR read stage 2 delay = 4-2-1 = 1 nop ) Cheers James
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