From: David Daney <david.daney@xxxxxxxxxx>
This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
There are two problems:
1) It breaks OCTEON, which will now crash in early boot with:
Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
2) The logic is broken.
The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
is required. The offending patch attempts (and fails) to change the
meaning to be that EHB is part of the ISA.
Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
---
arch/mips/mm/tlbex.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d75ff73..ff8d99c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -501,7 +501,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
case tlb_indexed: tlbw = uasm_i_tlbwi; break;
}
- if (cpu_has_mips_r2_exec_hazard) {
+ if (cpu_has_mips_r2) {
/*
* The architecture spec says an ehb is required here,
* but a number of cores do not have the hazard and
@@ -1953,7 +1953,7 @@ static void build_r4000_tlb_load_handler(void)
switch (current_cpu_type()) {
default:
- if (cpu_has_mips_r2_exec_hazard) {
+ if (cpu_has_mips_r2) {
uasm_i_ehb(&p);
case CPU_CAVIUM_OCTEON:
@@ -2020,7 +2020,7 @@ static void build_r4000_tlb_load_handler(void)
switch (current_cpu_type()) {
default:
- if (cpu_has_mips_r2_exec_hazard) {
+ if (cpu_has_mips_r2) {
uasm_i_ehb(&p);
case CPU_CAVIUM_OCTEON:
--
1.7.11.7
