Re: [PATCH RFC v2 41/70] MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction

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On 02/23/2015 02:03 PM, David Daney wrote:
On 01/16/2015 02:49 AM, Markos Chandras wrote:
From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>

MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the
EHB instruction is available or not. This is necessary for MIPS R6
which also supports the EHB instruction.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>

For the version of this patch currently in mips-for-linux-next: NACK


FYI, that would be: Commit id: 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed

There are two problems:

1) It breaks OCTEON, which will now crash in early boot with:

   Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)

2) The logic is broken.

The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
is required.  You change the meaning to be that EHB is part of the ISA.

Can we get this patch reverted from mips-for-linux-next?

David Daney


---
  arch/mips/mm/tlbex.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ff8d99ce3b9b..d75ff73a2012 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -501,7 +501,7 @@ static void build_tlb_write_entry(u32 **p, struct
uasm_label **l,
      case tlb_indexed: tlbw = uasm_i_tlbwi; break;
      }

-    if (cpu_has_mips_r2) {
+    if (cpu_has_mips_r2_exec_hazard) {
          /*
           * The architecture spec says an ehb is required here,
           * but a number of cores do not have the hazard and
@@ -1953,7 +1953,7 @@ static void build_r4000_tlb_load_handler(void)

          switch (current_cpu_type()) {
          default:
-            if (cpu_has_mips_r2) {
+            if (cpu_has_mips_r2_exec_hazard) {
                  uasm_i_ehb(&p);

          case CPU_CAVIUM_OCTEON:
@@ -2020,7 +2020,7 @@ static void build_r4000_tlb_load_handler(void)

          switch (current_cpu_type()) {
          default:
-            if (cpu_has_mips_r2) {
+            if (cpu_has_mips_r2_exec_hazard) {
                  uasm_i_ehb(&p);

          case CPU_CAVIUM_OCTEON:








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