On Mon, 1 Dec 2014, Måns Rullgård wrote: > > there is really on-chip RAM for AR7 at address 0. The AR7 CPU core > > is only MIPS32r1, so it doesn't have the exception vector base register > > and needs ram at physical address 0 for exception handlers (which all > > older cores do). I can't check right now, but even IP28 should have > > some memory mirrored there. The problem on IP28 is that accessing > > memory uncached requires reprogramming the memory controller (which > > then doesn't fit the concept of fast_iob()). > > Well, that explains why it works on AR7. It still doesn't tell me the > correct way to handle a 74k-based chip (MIPS32r2) with RAM starting at > physical address 0x04000000. I defined the thing long ago (circa 2000), before such configurations were of concern, under the assumption there must be readable storage that behaves like memory (i.e. safe to read, no side effects) at the base of KSEG0/KSEG1 because this is where the exception handlers reside. The definition should have been updated by whoever implemented support for newer processors for which the assumption does not stand anymore. For MIPSr2 and newer architectures you may define a variant that reads from CP0.EBase, masks out the unwanted fields and ORs in the KSEG1 bits. The natural way to implement this would be in C code, probably directly in the input operand's expression, replacing CKSEG1 hardcoded there now, so that the compiler can optimise the address calculation sequence (e.g. it can keep it around in a register rather than recalculating it every time if the piece is invoked repeatedly). FWIW I plan to rewrite our I/O barriers in an effort to make them portable across all Linux targets so that cross-platform drivers can use them. I think I outlined the plan sometime ago, on LKML or maybe netdev. Such low-level handlers like this will obviously stay, but names can change and definitions may be shuffled around. Right now we have quite a mess across various platforms whose access ordering strength varies for I/O (all the world is not PCI!), it's only memory access ordering strength handling that we've got nice and clean once DEC Alpha entered the game. Maciej
