Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx> writes: > On Sun, Nov 30, 2014 at 12:20:17PM +0000, Måns Rullgård wrote: >> My concern is over systems like AR7. It defines PHYS_OFFSET to >> 0x14000000 and UNCAC_BASE, correspondingly, to 0xb4000000. According to >> the linux-mips wiki, there is some on-chip RAM at physical address 0, >> which explains why the __fast_iob() macro works there. > > there is really on-chip RAM for AR7 at address 0. The AR7 CPU core > is only MIPS32r1, so it doesn't have the exception vector base register > and needs ram at physical address 0 for exception handlers (which all > older cores do). I can't check right now, but even IP28 should have > some memory mirrored there. The problem on IP28 is that accessing > memory uncached requires reprogramming the memory controller (which > then doesn't fit the concept of fast_iob()). Well, that explains why it works on AR7. It still doesn't tell me the correct way to handle a 74k-based chip (MIPS32r2) with RAM starting at physical address 0x04000000. -- Måns Rullgård mans@xxxxxxxxx
