Hello, 2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>: > It is not mine, I just fixed an existent code which applies a wrong errata > to 1074K. > Errata fix did exist before me. Are there any reasons why you cannot quote an internal note about this errata which would give a better idea of what this code is about? Sorry but the diff really does not help understand what is happening without a proper explanation of why this is required. At first glance it would like some revisions of the CPU are affected by some D$ bug? > > - Leonid. > > > > On 09/12/2013 08:12 AM, Paul Burton wrote: >> >> Agreed, my point is not about your code but your commit message. If I'm >> reading a commit which works around CPU errata I should not have to go and >> ask the hardware engineers or even read an errata document in order to know >> what you're doing. Your commit message should explain the errata, its >> effects and how your patch works around the problem. >> >> Paul >> >> On 12/09/13 16:05, Florian Fainelli wrote: >>> >>> 2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>: >>>> >>>> Treat it as is. >>>> >>>> It is a dirty laundry of HW engineers and you may need to communicate >>>> with them or read Errata docs on CPU. >>>> >>>> If it is about a way how it is written - ask Steven, initially it was in >>>> mainland probe code but he think it should be a separate function. I just >>>> corrected him, pointing that erratas on 74K and 1074K are different. But >>>> because he insist on having the same CPU_74K for both, so... >>> >>> If you take a look at another CPU company such as ARM, they provide >>> lengthy explanations for their various Erratas: >>> >>> config PJ4B_ERRATA_4742 >>> bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the >>> CPU Core to Cease Operation" >>> depends on CPU_PJ4B && MACH_ARMADA_370 >>> default y >>> help >>> When coming out of either a Wait for Interrupt (WFI) or a Wait >>> for >>> Event (WFE) IDLE states, a specific timing sensitivity exists >>> between >>> the retiring WFI/WFE instructions and the newly issued >>> subsequent >>> instructions. This sensitivity can result in a CPU hang >>> scenario. >>> Workaround: >>> The software must insert either a Data Synchronization Barrier >>> (DSB) >>> or Data Memory Barrier (DMB) command immediately after the >>> WFI/WFE >>> instruction >>> >>> I really think that you should aim for the same level of information >>> so that people know whether this is relevant for their platform, >>> whether they have the ECO applied etc... >> >> > > -- Florian
