2013/9/12 Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>:
> Treat it as is.
>
> It is a dirty laundry of HW engineers and you may need to communicate with them or read Errata docs on CPU.
>
> If it is about a way how it is written - ask Steven, initially it was in mainland probe code but he think it should be a separate function. I just corrected him, pointing that erratas on 74K and 1074K are different. But because he insist on having the same CPU_74K for both, so...
If you take a look at another CPU company such as ARM, they provide
lengthy explanations for their various Erratas:
config PJ4B_ERRATA_4742
bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the
CPU Core to Cease Operation"
depends on CPU_PJ4B && MACH_ARMADA_370
default y
help
When coming out of either a Wait for Interrupt (WFI) or a Wait for
Event (WFE) IDLE states, a specific timing sensitivity exists between
the retiring WFI/WFE instructions and the newly issued subsequent
instructions. This sensitivity can result in a CPU hang scenario.
Workaround:
The software must insert either a Data Synchronization Barrier (DSB)
or Data Memory Barrier (DMB) command immediately after the WFI/WFE
instruction
I really think that you should aim for the same level of information
so that people know whether this is relevant for their platform,
whether they have the ECO applied etc...
--
Florian
