CONFIG_CSRC_R4K is defined . However, I have not enabled CONFIG_CSRC_GIC and gic_present is initialized to 'zero' . I am a bit confused about CONFIG_SRC_GIC macros. I am not sure if GIC is an external timer outside the mips 34Kc core (specific to malta reference board)? In that case, we might have to replace to GIC source code with our own General purpose timer code. Can you please confirm if i am missing something here? It will be verfy helpful if you can explain a bit about the significance of CSRC_R4K & CSRC_GIC macros definitions in SMVP model.
We have been stuck with this issue for quiet sometime and looking for ways to resolve this at the best possible way. Your suggestions are really helpful in this regard.
Regards,
Jeffin
On Mon, Jul 30, 2012 at 8:22 PM, Steven J. Hill <sjhill@xxxxxxxxxxxxxxxxxx> wrote:
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>
> Synchronize counters across 2 CPUs: done. NET: Registered protocol family
> 16 bio: create slab <bio-0> at 0 Switching to clocksource MIPS
>
>
> As mentioned in my previous post, even with 3.4.2 kernel, the control
> loops in stop_machine_cpu_stop function. Do you suspect anything here? btw,
> if we set "clocksource=jiffies" in the bootargs, the system boot goes fine.
> The issue is observed only during switching from default clocksource to
> MIPS clocksource. Also, the boot works fine with 'nosmp=1' option & MIPS
> clocksource.
>
Make user that you select both CONFIG_CSRC_R4K ad CONFIG_CSRC_GIC for your
clock sources. The GIC counter will be used from synchronization across the
CPUs. Secondly, the hang is not actually a hard hang. Wait 50 seconds and I
bet you will see the boot complete.
- -Steve
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